Tools Needed

  • Quartus II Web Edition Software
  • ModelSim-Altera

Installation - Quartus II CAD

  1. Download Quartus II Web Edition Software
    • [Google Search: Quartus II]
    • Click Download
      • Current Version: Quartus II Web Edition v10.1
      • Download Windows Version (3.0 GB)
      • Click Continue Download in the pop-up window
      • Continues to Login page
    • Enter email address to Get One-Time Access for download center
      • Continue instructions to download file
  2. Run the file and extract the contents
  3. Continue with the installation process
    • Components to Install
      • Quartus II Web Edition
      • Cyclone II Family
    • TalkBack program - Don't need
  4. When Installation is done, don't need to get the Quartus II Subscription License

Installation - ModelSim

  1. Download ModelSim-Altera Starter Edition 6.6c Software for Quartus II Software Version 10.1
  2. Run the file and extract the contents
  3. Continue with the installation process
    • Install in the same directory as Quartus II CAD

Installation - USB Blaster Driver

Written for installing on Windows 7.
  1. Connect the DE1 board to the computer and power it on
  2. Under Devices and Printers, bring up the 'USB-Blaster' properties
  3. Hardware -> Properties -> Update Driver..
  4. Select Browse my computer for driver software (Locate and install driver software manually)
  5. Select Let me pick from a list of device drivers on my computer
  6. Choose Sound, video and game controllers
  7. Select Have Disk...
  8. Find usbblstr.inf under Browse and select OK
  9. Select Altera USB-Blaster and continue with the installation. Select Install Anyway for any warnings.

Lab 1

Supporting documents

Appendix B - Using Quartus II CAD (If you don't have the book yet)

Updates/Corrections for Version 10.1

B.3.1 - Using the Block Editor

No Changes

B.3.2 - Synthesizing a Circuit from the Schematic

Using the compiler

The compiler tools shown in the Appendix are not under Tools | Compiler Tool anymore.
  • These tools can be accessed from the Tasks window
  • They can be run one at a time by double-clicking on the individual tools
  • All of them can be run by double-clicking Compiler Design

Compilation Report - Equations

Equations are not displayed in the Compilation Report by default.
  • [Only needs to be done once]
  • Go to Tools -> Options..
  • In the options window, General -> Processing
    • select Automatically generate equation files during compilation
  • The equations can now be selected from the Compilation Report window

B.3.3 - Simulating the Designed Circuit

Quartus II doesn't have a native/build-in simulator in version 10.1 (Thus, no Waveform Editor).

Follow these steps to perform the functional simulation using ModelSim.

Performing the Simulation - Functional Simulation
  1. In Quartus II, convert your Block Diagram/Schematic file into Verilog HDL file.
    • File -> Create HDL Design File from Current File...

    • Select Verilog HDL and press OK.
  2. Open ModelSim
  3. In the Welcome Screen, Choose Jumpstart -> Create a Project
    • Give project a name
    • Choose the location of your design files as the Project Location. (Directory used for your file in Quartus II)
    • Leave the Default Library Name as 'work'
  4. In the Add Items to the Project window that pops up, Choose Add Existing File
    • Select the Verilog file (.v) created in Step 1
  5. Compile the Verilog file in ModelSim
    • In the Project window, right-click -> Compile -> Compile Selected
    • There should be a Green Arrow under Status after successful compilation
  6. Start Simulation
    • Simulate -> Start Simulation
    • Expand the library you created when you created the project and select your Verilog module
    • Select OK
  7. Add your input and output signals to the Wave window
    • Bring up the Wave window by View -> Wave
    • Drag the signals from the Objects window to the Wave window
      • or, right-click on wave -> Add -> To Wave -> Selected Signals
  8. Enter signal values using force (Source:
    • To enter a signal value on a step by step basis, select an input signal and right click on the pop-up; select Force and for value enter either 0 or 1. [Kind should be freeze, delay should be 0, cancel after should be blank.] Do this for all input signals.
    • In the tool icons, find the window that contains the period of the signal, e.g. 100ns. Immediately to the right of that window will be the run simulation icon (looks like a page with a blue down arrow beside it). Select run simulation. You should see the inputs that you entered and the outputs from your system on the waveform. The period of the run will correspond to the time in the period window. All signals should be green. If any signals are red, then one or more of the inputs was not specified.
    • Change one of the input signals. Select an input signal and right click on the pop-up; select Force and for value change the 0/1 to 1/0. Select run simulation.
    • Repeat until all combinations have been tested.
    • Immediately to the left of the signal period window is the restart simulation icon. Selecting restart will erase all signal values entered

  9. Optional: Alternatively, a DO file can be created to automate some of the processes in step 8
    1. Create a new DO file
      • File -> New -> Source -> DO
    2. Enter "procedural" steps in the DO file that corresponds to how you want the signals to change
      • Ask for instructions during Office Hours
    3. Execute the DO file
      • Enter do in VSIM> prompt

Lab 2

Supporting documents

Appendix B - Using Quartus II CAD (If you don't have the book yet)

Updates/Corrections for Version 10.1

B.4.4 & B.5 - Functional Simulation

For the simulation, use ModelSim (similar to lab 1).

No other changes.

B.6 - Quartus II Windows

No major changes.

Note: When simulating the mixed schematic design, make sure the modules that the top-level design refers to are also included in the ModelSim project. Otherwise, simulation will not load properly due to unresolved references.

Lab 3

Supporting Documents


Updates/Corrections for Version 10.1

C.1.2 - Compiling the project

Note: For the functional simulation in Lab 2, only 'Analysis & Synthesis' was needed to be run. In order to perform timing simulation:
  • we need to run the complete compilation
    • i.e. Analysis & Synthesis, Fitter, Assembler, etc
  • Double-click on Compile Design or Processing -> Start Compilation (Ctrl+L) to perform the complete compilation
Note: Fitter Equations can still be found in the Compilation Report -> Fitter section -> Equations

C.1.3 - Performing Timing Simulation

Similar to the previous labs, the timing simulation needs to be performed in ModelSim. Follow the following steps to perform the simulation.
  1. Set up the NativeLink Settings so that ModelSim-Altera can be automatically launched from Quartus II. (Only needs to be done once)
    1. Specify the location of the tool executable for ModelSim-Altera
      • Tools -> Options -> General -> EDA Tool Options
      • Provide the Location of Executable for ModelSim-Altera
        • For example: C:/altera/10.1/modelsim_ase/win32aloem
    2. Select ModelSim-Altera as the tool to be used for Simulation
      • Assignments -> Settings -> EDA Tool Settings -> Simulation
      • Under 'Tool Name' select 'ModelSim-Altera'
      • Format for output netlist: VHDL
        • Integration between Quartus II and ModelSim is better when using VHDL for netlist (no need for adding additional libraries in ModelSim)
      • Make sure 'Run gate-level simulation automatically after compilation' is checked.
        • If this is not checked, the simulation can be manually started after compilation is successful (Tool -> Run EDA Simulation Tool -> EDA Gate Level Simulation)
  2. Perform the complete compilation and make sure no errors are produced
  3. Since the gate-level simulation was configured to automatically run after compilation, the ModelSim will be launched automatically and configured for simulation
  4. In ModelSim, start the simulation
    1. Simulate -> start simulation...
    2. Under the 'work' library, select the top-level module in your design and select OK
  5. Similar to the previous labs, stimulate the input signals and run simulation. At this stage, the results look the "same" as the functional simulation

  6. To view the timing details (propagation delays, etc) in the waveform,
    • select 'Expanded Time Deltas Mode'
      • Wave -> Expanded Time -> Deltas Mode or press the shortcut button (view red arrow in the below image)
    • select 'Expand All Time' to see the delays (view orange arrow in the below image)
  7. To measure the transition times of the output, use the Find Previous/Next Transition button to move the cursors to the desired position
  8. Exit ModelSim when done.

USB Blaster Driver

Summary of instructions for installing the driver is located above in the Installation section

D.1 & D.2 - Making Pin Assignments and Uploading design to DE1 board

Follow the following tutorial written by previous EE 271 TA

Lab 4

No updates

Lab 5

Supporting Documents


Updates/Corrections for Version 10.1

Listed are the major tasks to be completed in Lab 5. The following is the summary of updates provided here for working the new version of Quartus II.
  1. Mapping sequential logic to the FPGA
    1. 'simple' module
      • Updates: Appendix C.5 has outdated instructions for performing timing simulation. Follow the instructions below to perform the simulation (and use the testbench file provided, to make your life easier!)
        • The implementation to the FPGA (compiling, port mapping, programming, etc.) should be same as previous labs
        • The code used should be the same as the one provided in the lab description
    2. 'clocked_design' module
      • Updates: None!
        • Clarification: there's no simulation to be performed for this module. Just compile, map the ports (clock, keys, and lights), program, and test.
  2. Runaway Lights
    1. Design the FSM
      • Updates:
        • None for the design.
        • For simulation of your design, use the testbench used for 'simple' module as a reference and write a testbench to test your FSM.
    2. Schematic of the FSM
      • Updates: None!

C.4 - Design of a Finite State Machine

Please follow the directions in Appendix C.4 up until the simulation part. Here's a summary of tasks to be completed before the simulation:
  • Start a new project and add the verilog file to implement the FSM shown in Figure C.32
    • Remember to use the verilog file provided in the lab description instead of the one in the appendix
  • Change the State Machine Processing to User-Encoded
  • Successful compilation of the project
Following are the steps to perform timing simulation using a testbench file:
  1. Download the following testbench file and save it the project directory
    • //Testbench file for Lab 5 EE 271
      //Arul Sekar

      `timescale 1ns/1ps    //sets the timescale to 1ns and the precision to 1ps

      module simple_test();
          reg clk, resetn, w;
          wire z;
          //create an instance of the simple module (UUT = Unit Under Test)
          simple UUT(clk, resetn, w, z);
          //make the clock cycle 100ns
              #50 clk = ~clk;
          //set the initial conditions
              clk = 0;
              resetn = 0;
              w = 0;
          //cycle through a combination of inputs
          //-changing values before the next posedge of the clock
          //-This could also be placed in the initial block if only needed to be run once
              @(negedge clk);    //wait till the next negedge
              resetn = 1;    //take off the reset
              @(negedge clk); //wait till the next negedge...
              w = 1;
              @(negedge clk);
              w = 0;
              @(negedge clk);
              w = 1;
              @(negedge clk);
              @(negedge clk);
              w = 0;
              @(negedge clk);
              w = 1;
              @(negedge clk);
              @(negedge clk);
              @(negedge clk);
              w = 0;
              @(negedge clk);
              @(negedge clk);
              @(negedge clk);
              @(negedge clk);
              @(negedge clk);


  2. Set the EDA Tool options if not already done
    • Tool -> Options -> EDA Tool Options
  3. Set the Simulation options
    • Assignments -> Settings -> EDA Tool Settings -> Simulation:
      • Tool Name: ModelSim-Altera
      • Format for output netlist: Verilog HDL
      • Time Scale: 1 ns
      • You may check 'Run gate-level simulation automatically after compilation'
        • if not, simulation can be manually started (Tool -> Run EDA Simulation Tool -> EDA Gate Level Simulation)
  4. Assign a test bench for the simulation
    1. Go to Assignments -> Settings -> EDA Tool Settings -> Simulation -> NativeLink Settings
    2. Select Compile test bench and then click on Test Benches...
    3. In the Test Benches window, select New...
    4. In the New Test Bench Settings, enter the following:
      • Test bench name: simple_test (or whatever you want)
      • Top level module in test bench: simple_test (should match testbench module name)
      • Simulation Period -> End simulation at: 1500 ns
      • Test bench files ->
        • File name: Browse and select the simple_test.v testbench file
        • Click Add to add the file
      • Select OK to add the new test bench
    5. Select OK in Test Benches window to use this test bench
    6. Results
      • New Test Bench Settings
      • Test Benches
  5. Perform full compilation and run the EDA Gate Level Simulation.
  6. If everything works, the ModelSim would be start and complete the simulation. 
    • Zoom out in the Wave window to get a good picture of the performed simulation
  7. To view the behavior of the internal state variables (implemented using flipflops 'lsb' and 'msb'), add the nodes to the wave window and run the simulation for more time to view the changes
    1. In the sim window, select the instance 'UUT'
    2. Then in the objects window, select '\lsb|q~regout' and '\msb|q~regout' and add them to the wave window
      • Arrange the signals such that msb|q is on top of lsb|q (useful in next step)
    3. Group the msb and lsb signals to view them as a single state value
      1. Highlight both the msb and lsb signals in the wave window
      2. Wave -> Combine signals...
        • Result name: state
        • Order to combine selected variables: Top down
        • Order of Result Indexes: Descending
        • Leave Flatten Arrays selected
    4. Run the simulation for another 1500 to view the behavior of the newly added signals
      • In the command window, type 'run 1500 ns'
      • To view the state as integers, right-click on 'state' signal -> Radix -> unsigned

  8. Close ModelSim when done with simulation
Continue with the Appendix tutorial when done with simulation. The Compilation Report is presented in a similar manner to the previous version of Quartus II; therefore, no major updates for analyzing the Timing summary, Flow summary, etc.