Notes on learning PIC18Fxx2 (specifically, PIC18F452)
PIC18FXX2
Supporting Documents
Obtained from http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en010296Datasheet
https://sites.google.com/a/arulsekar.com/www/learning/pic18/pic18fxx2-datasheet.pdf
PIC18452
Summary
40-pin High Performance, Enhanced FLASH Microcontroller with 10-Bit A/D- RISC CPU
- C compiler optimized architecture/instruction set
- Instructions: 16-bit
- Instruction Set: 75 instructions
- Data: 8-bit
- program memory addressing to 32 Kbytes
- data memory addressing to 1.5 Kbytes
- Priority level for Interrupts
- Memory Details
- Flash, RAM, EEPROM...
- Technology
- CMOS...
Features
- 3 external interrupt pins
- 18 total interrupt sources
- I/O ports
- A, B, C, D, E
- Timer0
- 8/16-bit timer or counter
- 8-bit prescaler
- Timer1
- 16-bit timer or counter
- Timer2
- 8-bit timer or counter
- 8-bit period register
- Timer3
- 16-bit timer or counter
- 2 CCP modules
- capture/compare/PWM
- MSSP module (Serial Comm.)
- Master Synchronous Serial Port
- SPI/I2C
- USART module (Serial Comm.)
- Addressable
- RS-232/RS-485
- PSP Module (Parallel Comm.)
- Parallel Slave Port
- ADC Module
- 10-bit
- 8-input channels
- available during sleep
- PLVD
- Programmable Low Voltage Detection
- can generate interrupt
- BOR
- Programmable Brown-out Reset
- POR
- Power-on Reset
- PWRT
- Power-up Timer
- OST
- Oscillator Start-up Timer
- WDT
- Watchdog Timer
- Sleep Mode
- Selectable Oscillator Options
- primary/secondary
- In-Circuit Serial Programming
- In-Circuit Debugging
Pin Diagram
- Ground Reference for logic and I/O
- MCLR
- Master Clear (Reset) input
- active low
- Vpp
- for programming (TODO)
- OSC1
- oscillator crystal input
- CLKI
- External clock sourse input
- OSC2
- oscillator crystal output
- CLKO
- outputs OSC1 clock freq/4
- only when in RC mode
- i.e. instruction cycle rate
- RA6
- see below
- RAx
- Digital I/O
- TTL buffer
- ANx
- Analog input
- Vref+/-
- RA4 - Open drain output
- T0CKI
- RA5 - !SS, LVDIN
- RA6 - OSCstuff
- Digital I/O
- TTL buffer
- Internal weak pull-ups available
- enabled via software
- External interrupt INT0-2
- Interrupt on change pins (RB4-7)
- Programming pins
- CCP2 pin (RB3)
- Digital I/O
- Schmitt Trigger input with CMOS levels
- Timerx pins
- CCPx pins
- SCK, SCL, SDI, SDO, SDA
- for SPI and I2C
- TX, RX, CK, DT
- for USART
- Digital I/O
- Schmitt Trigger input with CMOS levels
- PSPx
- Parallel Slave Port data
- TTL Input buffers
- for interfacing to a microprocessor port
- Digital I/O
- Schmitt Trigger input with CMOS levels
- Addn. controls for PSP
- Analog input 7
Block Diagram
https://sites.google.com/a/arulsekar.com/www/learning/pic18/pic18fxx2-blockdiagram.pdfBreakdown
Oscillator Configuration
8 different modes3 configuration bits to select mode
External Clock mode
An external clock source is connected to OSC1 pinStartup time details (See below)
With EC mode, OSC2 outputs clockfreq/4
With ECIO mode, OSC2 becomes digital I/O port (RA6)
Power-up Delays
TODOResets
asdfMemory - Program Memory
- Uses a separate bus from data memory
- for concurrent access
- 32 KBytes of FLASH memory
- i.e. can store 16K single-word instructions
- 21-bit Program Counter is used for access
- i.e. can access 2MBytes of memory
- trying to access memory beyond the physically implemented memory (32KBytes) results in NOP instruction (all 0s)
Organization
Accessing
Memory - Return Address Stack
asdfMemory - Data RAM
- 4096 bytes of static RAM
- Each register has 12-bit address
- Divided into 16 banks
- each contains 256 bytes
- BSR's (Bank Select Register) lower 4 bits are used for selecting bank
Organization
SFR: Special Function Registers- control and status of the controller and peripheral functions
- start at last location of Bank 15 (0xFFF) and extend downwards
- Data storage and scratch pad operations during application execution
- start at first location of Bank 0 and grow upwards
- To ensure commonly used registers can be accessed in a single cycle
- TODO
Addressing
TODOMemory - Data EEPROM
adsf
